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preliminary 3.3v programmable skew clock buffe r cy7c9915 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07687 rev. ** revised june 25, 2004 features ? all output pair skew <100 ps (typical) ? input frequency range: 3.75 mhz to 150 mhz ? output frequency range: 3.75 mhz to 150 mhz ? user-selectable output functions ? selectable skew to 18 ns ? inverted and non-inverted ? operation at 1 ? 2 and 1 ? 4 input frequency ? operation at 2x and 4x input frequency (input as low as 3.75 mhz) ? zero input-to-output delay ? 3.3v power supply ? 2.5% output duty cycle distortion ? lvttl outputs drive 50 ? terminated lines ? low operating current ? 32-pin plcc package ? jitter < 100ps peak-to-peak (< 15 ps rms) functional description the cy7c9915 roboclock is a 150-mhz low-voltage programmable skew clock buffer that offers user-selectable control over system clock function s. this multiple-output clock driver provides the system inte grator with functions necessary to optimize the timing of high-performance computer systems. eight individual drivers, arranged as four pairs of user-control- lable outputs, can each drive terminated transmission lines with impedances as low as 50 ? while delivering minimal and specified output skews and full-swing logic levels (lvttl). each output can be hardwired to one of nine delay or function configurations. delay increments of 0.42 to 1.6 ns are deter- mined by the operating frequency with outputs able to skew up to 6 time units from their nominal ?zero? skew position. the completely integrated pll allows external load and trans- mission line delay effects to be canceled. when this ?zero delay? capability of the lvpscb is combined with the selectable output skew func tions, the user can create output-to-output delays of up to 12 time units. divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. when combined with the internal pll, these divide functions allow distribution of a low-frequency clock that can be multi- plied by two or four at the cl ock destination. this facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. block diagram pin configuration test fb ref vco and time unit generator fs select inputs (three level) skew select matrix 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 filter phase freq det cy7c9915 30 31 32 1 2 3 4 3f0 vccq fs ref gnd test 2f1 20 19 18 17 16 15 14 3q1 vccn3 3q0 fb vccn2 2q1 2q0 5 6 7 8 9 10 11 12 13 3f1 4f1 4f0 vccq vccn4 4q1 4q0 gnd gnd 29 28 27 26 25 24 23 22 21 2f0 1f1 gnd 1f0 vccn1 1q0 1q1 gnd gnd
preliminary cy7c9915 document #: 38-07687 rev. ** page 2 of 13 block diagram description phase frequency detector and filter these two blocks accept inputs from the reference frequency (ref) input and the feedback (fb) input and generate correction information to control the frequency of the voltage-controlled oscillator (v co). these blocks, along with the vco, form a phase-locked loop (pll) that tracks the incoming ref signal. vco and time unit generator the vco accepts analog control inputs from the pll filter block and generates a frequency that is used by the time unit generator to create discrete time units that are selected in the skew select matrix. the operational range of the vco is deter- mined by the fs control pin. the time unit (t u ) is determined by the operating frequency of th e device and the level of the fs pin as shown in table 1 . skew select matrix the skew select matrix is comprised of four independent sections. each section has two low-skew, high-fanout drivers (xq0, xq1), and two corresponding three-level function select (xf0, xf1) inputs. table 2 below shows the nine possible output functions for each sectio n as determined by the function select inputs. all times are measured with respect to the ref input assuming that the output connected to the fb input has 0t u selected. notes: 1. for all three-state inputs, high indicates a connection to v cc , low indicates a connection to gnd, and mid indicates an open connection. internal termination circuitry holds an unconnected input to v cc /2. 2. the level to be set on fs is determined by the ?normal? operating frequency (f nom ) of the v co and time unit generator (see logic block diagram). nominal frequency (f nom ) always appears at 1q0 and the other outputs when they are operated in their undivided modes (see table 2 ). the frequency appearing at the ref and fb inputs will be f nom when the output connected to fb is undivided. the frequency of the ref and fb inputs will be f nom /2 or f nom /4 when the part is configured for a frequency multiplication by using a divided output as the fb input. pin definitions (cy7c9915) pin no. name i/o type description 1 ref input lvttl/lvcmos reference clock input 17 fb input lvttl feedback clock input 3 fs input three-level three level frequency range select 26,27 1f0, 1f1 input three-level three level function select for 1q0,1q1 29,30 2f0, 2f1 input three-level three level function select for 2q0,2q1 4,5 3f0, 3f1 input three-level three level function select for 3q0,3q1 6,7 4f0, 4f1 input three-level three level function select for 4q0,4q1 31 test input three-level three le vel select for test modes 23,24 1q0, 1q1 output lvttl output pair 19,20 2q0, 2q1 output lvttl output pair 14,15 3q0, 3q1 output lvttl output pair 10,11 4q0, 4q1 output lvttl output pair 25 vccn1 power power 3.3v power supp ly for output pair 1q0 and 1q1. 18 vccn2 power power 3.3v power supply for output pair 2q0 and 2q1. 16 vccn3 power power 3.3v power supp ly for output pair 3q0 and 3q1. 9 vccn4 power power 3.3v power supply for output pair 4q0 and 4q1. 2,8 vccq power power 3.3v core power 12,13,21,22, 28, 32 gnd ground power ground table 1. frequency range select and t u calculation [1] fs [2] f nom (mhz) where n = approximate frequency (mhz) at which t u = 1.0 ns min. max. low 15 30 44 22.7 mid 25 50 26 38.5 high 40 150 16 62.5 t u 1 f nom n ---------------------- - - =
preliminary cy7c9915 document #: 38-07687 rev. ** page 3 of 13 note: 3. fb connected to an output selected for ?zero? skew (i.e., xf1 = xf0 = mid). table 2. programmable skew configurations [1] function selects output functions 1f1, 2f1, 3f1, 4f1 1f0, 2f0, 3f0, 4f0 1q0, 1q1, 2q0, 2q1 3q0, 3q1 4q0, 4q1 low low ?4t u divide by 2 divide by 2 low mid ?3t u ?6t u ?6t u low high ?2t u ?4t u ?4t u mid low ?1t u ?2t u ?2t u mid mid 0t u 0t u 0t u mid high +1t u +2t u +2t u high low +2t u +4t u +4t u high mid +3t u +6t u +6t u high high +4t u divide by 4 inverted figure 1. typical outputs with fb connected to a zero-skew output [3] t 0 ? 6t u t 0 ? 5t u t 0 ? 4t u t 0 ? 3t u t 0 ? 2t u t 0 ? 1t u t 0 t 0 +1t u t 0 t 0 t 0 t 0 t 0 +2t u +3t u +4t u +5t u +6t u fbinput refinput ? 6t u ? 4t u ? 3t u ? 2t u ? 1t u 0t u +1t u +2t u +3t u +4t u +6t u divided invert lm lh (n/a) ml (n/a) mm (n/a) mh (n/a) hl hm ll/hh hh 3fx 4fx (n/a) ll lm lh ml mm mh hl hm hh (n/a) (n/a) (n/a) 1fx 2fx
preliminary cy7c9915 document #: 38-07687 rev. ** page 4 of 13 test mode the test input is a three- level input. in normal system operation, this pin is con nected to ground, allowing the cy7c9915 to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied low through a 100 ? resistor. this will allow an external test er to change the state of these pins.) if the test input is forced to it s mid or high st ate, the device will operate with its internal phase locked loop disconnected, and input levels supplied to ref will directly control all outputs. relative output to output functions are the same as in normal mode. in contrast with normal operatio n (test tied low). all outputs will function based only on the connection of their own function select inputs (xf0 and xf1) and the waveform characteristics of the ref input. operational mode descriptions figure 2 shows the lvpscb configur ed as a zero-skew clock buffer. in this mode the cy7c9915 can be used as the basis for a low-skew clock distribution tree. when all of the function select inputs (xf0, xf1) are le ft open, the outputs are aligned and may each drive a terminated transmission line to an independent load. the fb input can be tied to any output in this configuration and the operating frequency range is selected with the fs pin. the low-skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ? ), allows efficient printed circuit board design. figure 2. zero-skew and/or zero-delay clock driver system clock l1 l2 l3 l4 length l1 = l2 = l3 = l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test z 0 load load load load ref z 0 z 0 z 0 figure 3. programmable-skew clock driver length l1 = l2 l3 < l2 by 6 inches l4 > l2 b y 6 inches sys- tem clock l1 l2 l3 l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test z 0 load load load load ref z 0 z 0 z 0
preliminary cy7c9915 document #: 38-07687 rev. ** page 5 of 13 figure 3 shows a configuration to equalize skew between metal traces of different lengths. in addition to low skew between outputs, the lvpscb ca n be programmed to stagger the timing of its outputs. the four groups of output pairs can each be programmed to different output timing. skew timing can be adjusted over a wide range in small increments with the appropriate strapping of the functi on select pins. in this config- uration the 4q0 output is fed back to fb and configured for zero skew. the other three pairs of outputs are programmed to yield different skews relative to the feedback. by advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time. in this illustration the fb inpu t is connected to an output with 0-ns skew (xf1, xf0 = mid) selected. the internal pll synchronizes the fb and ref inputs and aligns their rising edges to insure that all outp uts have precise phase alignment. clock skews can be advanced by 6 time units (t u ) when using an output selected for zero skew as the feedback. a wider range of delays is possible if the output connected to fb is also skewed. since ?zero skew?, +t u , and ?t u are defined relative to output groups, and since the pll aligns the rising edges of ref and fb, it is possible to create wider output skews by proper selection of the xfn inputs. for example a +10 t u between ref and 3qx can be achieved by connecting 1q0 to fb and setting 1f0 = 1f1 = gnd, 3f0 = mid, and 3f1 = high. (since fb aligns at ?4 t u and 3qx skews to +6 t u , a total of +10 t u skew is realized.) many other config- urations can be realized by skewing both the output used as the fb input and skewing t he other outputs. figure 4 shows an example of the invert function of the lvpscb. in this example the 4q 0 output used as the fb input is programmed for invert (4f0 = 4f1 = high) while the other three pairs of outputs are programmed for zero skew. when 4f0 and 4f1 are tied high, 4q0 and 4q1 become inverted zero phase outputs. the pll aligns the rising edge of the fb input with the rising edge of the ref. this causes the 1q, 2q, and 3q outputs to become the ?i nverted? outputs with respect to the ref input. by selecting wh ich output is connect to fb, it is possible to have 2 inverted and 6 non-inverted outputs or 6 inverted and 2 non-inverted out puts. the correct configu- ration would be determined by the need for more (or fewer) inverted outputs. 1q, 2q, and 3q outputs can also be skewed to compensate for varying trace delays independent of inversion on 4q. figure 5 illustrates the lvpscb conf igured as a clock multi- plier. the 3q0 output is programmed to divide by four and is fed back to fb. this causes the pll to increase its frequency until the 3q0 and 3q1 outputs are locked at 20 mhz while the 1qx and 2qx outputs run at 80 mhz. the 4q0 and 4q1 outputs are programmed to divide by two, which results in a 40-mhz waveform at these outputs. note that the 20- and 40-mhz clocks fall simultaneously and are out of phase on their rising edge. this will allow the designer to use the rising edges of the 1 ? 2 frequency and 1 ? 4 frequency outputs without concern for rising-edge skew. the 2q0, 2q1, 1q0, and 1q1 outputs run at 80 mhz and are skewed by programming their select inputs accordingly. note that the fs pin is wired for 80-mhz operation because that is the frequency of the fastest output. figure 6 demonstrates the lvpscb in a clock divider appli- cation. 2q0 is fed back to the fb input and programmed for zero skew. 3qx is programmed to divide by four. 4qx is programmed to divide by two. note that the falling edges of the 4qx and 3qx outputs are aligned. this allows use of the rising edges of the 1 ? 2 frequency and 1 ? 4 frequency without concern for skew mismatch. the 1qx outputs are programmed to zero skew and are aligned with the 2qx outputs. in this example, the fs input is grounded to configure the device in the 15- to figure 4. inverted output connections fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref figure 5. frequency multiplier with skew connections figure 6. frequency divider connections fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 20 mhz 20 mhz 40 mhz 80 mhz fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 20 mhz 5 mhz 10 mhz 20 mhz
preliminary cy7c9915 document #: 38-07687 rev. ** page 6 of 13 30-mhz range since the highest frequency output is running at 20 mhz. figure 7 shows some of the functions that are selectable on the 3qx and 4qx outputs. these include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. an inverted output allows the system designer to clock different subsystems on opposite edges, without suffering from the pulse asymmetry typical of non-ideal loading. this function allows the two subsystems to each be clock ed 180 degrees out of phase, but still to be aligned within the skew spec. the divided outputs offer a zero-delay divider for portions of the system that need the clock to be divided by either two or four, and still remain within a narrow skew of the ?1x? clock. without this feature, an exte rnal divider would need to be added, and the propagation delay of the divider would add to the skew between the different clock signals. these divided outputs, coupled with the phase locked loop, allow the lvpscb to mu ltiply the clock rate at the ref input by either two or four. this mode will enable the designer to distribute a low-frequency clock between various portions of the system, and then locally multiply the clock rate to a more suitable frequency, while still maintaining the low-skew charac- teristics of the clock driver. the lvpscb can perform all of the functions described above at the same time. it can multiply by two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. figure 7. multi-function clock driver figure 8. board-to-board clock distribution 27.5-mhz distribution clock 110-mhz inverted z 0 27.5-mhz 110-mhz zero skew 110-mhz skewed ?2.273 ns (?4t u ) fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref load load load load z 0 z 0 z 0 system clock z 0 l1 l2 l3 l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 ref fs fb load load load load load test z 0 z 0 z 0
preliminary cy7c9915 document #: 38-07687 rev. ** page 7 of 13 figure 8 shows the cy7c9915 connected in series to construct a zero-skew clock distribution tree between boards. delays of the downstream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero-delay clock tree. cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering characteristics of the pll filter. it is recommended that not more than two clock buffers be connected in series.
preliminary cy7c9915 document #: 38-07687 rev. ** page 8 of 13 absolute maximum conditions parameter description condition min. max. unit v dd supply voltage nonfunctional ?0.5 4.6 vdc v in input voltage ref relative to v cc ?0.5 4.6 vdc v in input voltage except ref relative to v cc ?0.5 v dd + 0.5 vdc lu i latch-up immunity functional 300 ma t s temperature, storage nonfunctional ?65 +125 c t a temperature, operating ambien t commercial temperature 0 +70 c t a temperature, operating ambient i ndustrial temperature ?40 +85 c t j junction temperature indu strial temperature 125 c ? jc dissipation, junction to case functional tbd c/w ? ja dissipation, junction to ambient functional tbd c/w esd h esd protection (human body model) 2000 v m sl moisture sensitivity level msl ? 1 class g ates total functional gate count assembled die tbd each ul?94 flammability rating @ 1/8 in. v?0 class fit failure in time manufacturing test 10 ppm t pu power-up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms c in input capacitance [4] t a = 25 c, f = 1 mhz, v cc = 3.3v ? 10 pf z out output impedance low to high (rising edge) 27 ? high to low (falling edge) 7 ? electrical characteristics over the operating range [5] parameter description cy7c9915 unit test conditions min. max. v ccq core power supply @3.3v 10% 2.97 3.63 v v ccn[1:4] output buffer power supply @3.3v 10% 2.97 3.63 v v oh output high voltage v cc = min., i oh = ?20 ma 2.4 ? v v ol output low voltage v cc = min., i ol = 36 ma ? 0.45 v v ih input high voltage (ref and fb inputs only) [6] 2.0 v cc v v il input low voltage (ref and fb inputs only) [6] ?0.5 0.8 v v ihh three-level input high voltage (test, fs, xfn) [7] min. v cc max. 0.87 * v cc v cc v v imm three-level input mid voltage (test, fs, xfn) [7] min. v cc max. 0.47 * v cc 0.53 * v cc v v ill three-level input low voltage (test, fs, xfn) [7] min. v cc max. 0.0 0.13 * v cc v i ih input high leakage current (ref and fb inputs only) v cc = max., v in = max. ? 10 a notes: 4. applies to ref and fb inputs only. tested initially and after an y design or process changes that may affect these parameters. 5. see the last page of this specification for group a subgroup testing information. 6. v ih and v il for fb inputs guaranteed by statistical correlation. tested initia lly and after any design or process changes that may affect this parameters.
preliminary cy7c9915 document #: 38-07687 rev. ** page 9 of 13 i il input low leakage current (ref and fb inputs only) v cc = max., v in = 0.4v ?10 ? a i ihh input high current (test, fs, xfn) v in = v cc ?200 a i imm input mid current (test, fs, xfn) v in = v cc /2 ? 50 50 a i ill input low current (test, fs, xfn) v in = gnd ? ? 200 a i os short circuit current [8] v cc = max, v out = gnd (25 only) ? ?200 ma i ccq operating current used by internal circuitry v ccn = v ccq = max., all input selects open com?l ? 90 ma mil/ind ? 100 i ccn output buffer current per output pair [9] v ccn = v ccq = max., i out = 0 ma input selects open, f max ?14ma pd power dissipation per output pair [10] v ccn = v ccq = max., i out = 0 ma input selects open, f max ?78mw electrical characteristics over the operating range (continued) [5] parameter description cy7c9915 unit test conditions min. max. ac test loads and waveforms ac input specifications parameter description condition min. max. unit t r ,t f input rise/fall edge rate 0.8v ? 2.0v ? 10 ns/v t pwc input clock pulse high or low 2 ? ns t dcin input duty cycle pll 10 90 % test mode 30 70 f ref reference input frequency fs=low 3.75 30 mhz fs=mid 6.25 50 fs=high 10 150 [11] notes: 7. these inputs are normally wired to v cc , gnd, or left unconnected (actual thres hold voltages vary as a percentage of v cc ). internal termination resistors hold unconnected inputs at v cc /2. if these inputs are switched, the func tion and timing of the outputs may glitch and the pll may require an additional t lock time before all data sheet limits are achieved. 8. cy7c9915 should be tested one output at a time, output shorted for le ss than one second, less than 10% duty cycle. room tempe rature only. 9. total output current per output pair can be approximated by the following expression that includes device current plus load c urrent: cy7c9915:i ccn = [(4 + 0.11f) + [[((835 ?3f)/z) + (.0022fc)]n] x 1.1 where f = frequency in mhz c = capacitive load in pf z = line impedance in ohms n = number of loaded outputs; 0, 1, or 2 fc = f ? c 10. total power dissipation per output pair can be approximated by the following expression that includes device power dissipati on plus power dissipation due to the load circuit: pd = [(22 + 0.61f) + [[(1550 + 2.7f)/z) + (.0125fc)]n] x 1.1 see note 9 for variable definition. 11. in test mode, max ref input frequency is 133mhz. ttl ac test load ttl input test waveform v cc r1 r2 c l 3.0v 2.0v v th =1.5v 0.8v 0.0v 1ns 1ns 2.0v 0.8v v th =1.5v r1=100 r2=100 c l =30pf (includes fixture and probe capacitance)
preliminary cy7c9915 document #: 38-07687 rev. ** page 10 of 13 switching characteristics over the operating range [2, 12] parameter descripti on min. typ. max. unit f nom operating clock frequency in mhz fs = low [1, 2] 15 ? 30 mhz fs = mid [1, 2] 25 ? 50 fs = high [1, 2 ] 40 ? 150 f out output frequency fs=low 3.75 ? 30 mhz fs=mid 6.25 ? 50 fs=high 10 ? 150 f vco vco frequency 160 ? 650 mhz f bw loop bandwidth ? 1 ? mhz t u programmable skew unit see table 1 t skewpr zero output matched- pair skew (xq0, xq1) [13, 15] ?0.050.1ns t skew0 zero output skew (all outputs) [13, 16,17] ?0.10.2ns t skew1 output skew (rise-rise, fall-fall, same class outputs) [13, 18] ?0.250.3ns t skew2 output skew (rise-fall, no minal-inverted, divided-divided) [13, 18] ?0.30.5ns t skew3 output skew (rise-rise, fall-fall, different class outputs) [13, 18] ?0.250.5ns t skew4 output skew (rise-fall, nominal-divided, divided-inverted) [13, 18] ?0.50.9ns t dev device-to-device skew [14, 19] ? ? 0.75 ns t pd propagation delay, ref rise to fb rise ?0.15 ? +0.15 ns t odcv output duty cycle variation [20] 47.5 50 52.5 % t pwh output high time variation [21] 47.5 50 52.5 % t pwl output low time variation [21] 47.5 50 52.5 % t orise output rise time [21, 22] 0.15 1.0 1.5 ns t ofall output fall time [21, 22] 0.15 1.0 1.5 ns t lock pll lock time [23] ??0.5ms t jr cycle-to-cycle output jitter rms [14] ??15ps peak-to-peak [14] ??100ps t pj period jitter rms [14] ??25ps peak-to-peak [14] ??150ps t phj phase jitter peak-to-peak [14] ??100ps notes: 12. test measurement levels for the cy7c9915 are ttl levels (1.5v to 1.5v). test conditions assume signal transition times of 2 ns or less and output loading as shown in the ac test loads and wavefo rms unless otherwise specified. 13. skew is defined as the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with 30 pf and terminated with ttlac test load. 14. guaranteed by statistical correlation. tested initially and after any design or process changes that may affect these parame ters. 15. t skewpr is defined as the skew between a pair of outputs (xq0 and xq1) when all eight outputs are selected for 0t u . 16. t skew0 is defined as the skew between outputs when they are selected for 0t u . other outputs are divided or inverted but not shifted. 17. c l =0 pf. for c l =30 pf, t skew0 =0.35 ns. 18. there are three classes of outputs: nominal (multiple of t u delay), inverted (4q0 and 4q1 only with 4f0 = 4f1 = high), and divided (3qx and 4qx only in divide-by-2 or divide-by-4 mode). 19. t dev is the output-to-output skew between any two devices operating under the same conditions (v cc ambient temperature, air flow, etc.) 20. t odcv is measure at v ccn/ 2. 21. specified with outputs loaded with 30 pf.cy7c9915. devices are terminated through 50 ? to v cc /2. t pwh is measured at 2.0v. t pwl is measured at 0.8v. 22. t orise and t ofall measured between 0.8v and 2.0v. 23. t lock is the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits.
preliminary cy7c9915 document #: 38-07687 rev. ** page 11 of 13 ac timing diagrams ordering information ordering code package type operating range cy7c9915-2jxc 32-lead plcc commercial, 0c to 70c cy7c9915-2jxi 32-lead plcc industrial, ?40c to 85c cy7c9915-5jxc 32-lead plcc commercial, 0c to 70c cy7c9915-5jxi 32-lead plcc industrial, ?40c to 85c t odcv t odcv t ref ref fb q other q inverted q ref divided by 2 ref divided by 4 t rpwh t rpwl t pd t skewpr, t skew0, 1 t skewpr, t skew0, 1 t skew2 t skew2 t skew3, 4 t skew3, 4 t skew3, 4 t skew1,3, 4 t skew2, 4 t jr
preliminary cy7b9915 document #: 38-07687 rev. ** page 12 of 13 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawing and dimensions all product and company names ment ioned in this document are trademarks of their respective holders. 32-lead plastic leaded chip carrier j65 51-85002-*b
preliminary cy7c9915 document #: 38-07687 rev. ** page 13 of 13 document history page document title: cy7c9915 3.3v programmable skew clock buffer document number: 38-07687 rev. ecn no. issue date orig. of change description of change ** 236268 see ecn rgl new data sheet

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